INTERLINE DYNAMIC VOLTAGE RESTORER PDF

Then a new device which is named Inter-line Dynamic Voltage Restorer (IDVR) is discussed. This device consists of two conventional DVRs which are installed. An interline dynamic voltage restorer (IDVR) is a novel c o m p e n s a t i o n piece of mitigation It is made of several dynamic voltage restorers (DVRs) with a. Index Terms—Dynamic voltage restorer, Interline dynamic voltage restorer, Current source inverter, SMES and Power quality.

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Electronics Nuclear engineering, Electrical and Electronic Engineering. The DF of the sourcing feeder increases while the DF of the receiving feeder decreases. This technique results in less energy being taken out of the DC-link capacitor, resulting in smaller size requirements. Strathprints home Open Access Login. Investigating the IDVR performance when the proposed method is applied for a sag with depth of 0.

Computer planning and simulation of power systems require system components to be represented mathematically. This paper deals with improving the voltage quality of sensitive loads from voltage sags using dynamic voltage restorer DVR. A method for building a dynamic phasor model of an Interline Dynamic Voltage Restorer IDVR is presented, and the resulting model is tested in a simple radial distribution system.

Interline dynamic voltage restorer (IDVR) Archives – ASOKA TECHNOLOGIES

This study aims to enhance the abilities of DVRs to maintain acceptable voltages and last longer during compensation. Then, more of the energy stored in the DC-link capacitor was utilized quickly, reaching its limitation within a shorter period.

An IDVR merely consists of several dynamic voltage restorers DVRs sharing a common dc link connecting independent feeders to secure electric power to critical loads.

In this case, the DF of the sourcing feeder will have a notable improvement with only a slight variation in DF of the receiving feeder. Resyorer the compensation was conducted using the proposed technique, less energy was used for the converter basic switching process.

Single line diagram of an IPFC in transmission system.

The main conclusions of this work can be summarized as follows: The overall three-phase voltage signals during zero-real power tracking compensation simulation. To overcome this limitation, a new interlinf is restoter in this paper which voltate to reduce the load power factor under sag condition, and therefore, the compensation capacity is increased. With this technique, none or less of the real power will be transferred to the system, which provides more for the DVR to cover a wider range of voltage dyjamic, adding more flexible adaptive control to the solution of sag voltage disturbances.

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The real and reactive powers are calculated in real time in the tracking loop to achieve better conditions. In this paper, a new configuration has been proposed which not only improves the compensation capacity of the IDVR at high power factors, but also increases the performance of the compensator to mitigate deep sags at fairly moderate power factors.

The experimental test results match those proposed using simulation, although some discrepancies due to the imperfect nature of the test circuit components were seen. Winter Meetingvol. DF improvement can be achieved via active and reactive power exchange PQ sharing between different feeders.

The performance of proposed method is evaluated using simulation study. The ensure compatibility with transient stability programs, the analysis is performed for the fundamental frequency only, with other frequency components being truncated and without considering harmonics. Mathematical analysis is carried out for each individual component of the IDVR as interlinf models, which are then aggregated to generate the final model.

The proposed technique has the advantage of simplifying the modelling of any volfage AC transmission system FACTS device in dynamic phasor mode when compared to other modelling techniques reported in the literature.

The overall three-phase voltage signals during in-phase compensation simulation.

For normal voltage levels, the DVRs should be bypassed. These advantages were achieved by decreasing the load power factor during sag condition.

Abojlala, Khaled Issa and Holliday, Derrick and Xu, Lie Transient analysis of interline dynamic voltage restorer using dynamic phasor representation. In this mode, theDFof one of the feeders is improved via active and reactive power exchange PQ sharing between feeders through the common dc link. The main conclusions of this work can be summarized as follows:.

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Per-phase simulation results for voltage sag condition at: Per-phase experimental and corresponding simulation results for DF improvement case: In this paper, an enhanced sag compensation strategy is proposed that mitigates restoder phase jump in the load voltage while improving the overall sag compensation time.

These operational constraints have been identified and considered. It is clear from both the simulation and experimental results illustrated in this paper that the proposed zero-real power tracking technique applied to DVR-based compensation can result in superior performance compared to the traditional in-phase technique.

The experimental results demonstrate the feasibility of the proposed phase jump compensation method for practical applications. While one of the DVRs compensates for the local voltage sag in its feeder, the other DVRs replenish the common dc-link voltage. In this paper an enhanced sag compensation scheme is proposed for capacitor supported DVR.

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This paper proposes a new operational mode for the IDVR to improve the DF of different feeders under normal operation. The compensation was eventually forced to stop before the entire voltage sag period was finished. The existing control strategies either mitigate the phase jump or improve the utilization of dc link energy by i reducing the amplitude of injected voltage, or ii optimizing the dc bus energy support.

IDVR compensation capacity, however, depends greatly on the load power factor and a higher load power factor causes lower performance of IDVR.

The results from both the simulation and experimental tests illustrate that the proposed technique clearly achieved superior performance. It also increases compensation time by operating in minimum active power mode through a controlled transition once the phase jump is compensated.

Instead of bypassing the DVRs in normal conditions, this paper proposes operating the DVRs, if needed, to improve the displacement factor DF of one of the involved feeders.